As integrated circuits continue to scale downward in size, the finFET (fin field effect transistor) is becoming an attractive device for use in semiconductor integrated circuits (ICs). In a finFET, the channel is formed by a semiconductor vertical fin, and a gate electrode is located and wrapped around the fin. With finFETs, as with other transistor types, the contacts that connect the source, drain, and gate of the transistor are an important factor in the production of smaller integrated circuits with desired performance and reliability characteristics. It is therefore desirable for cost reasons to push the limits of single patterning in the advanced CMOS nodes at 14 nm and below. Indeed, multiple patterning in the absence of production-worthy EUV lithography equipment is cost prohibitive and results in a paradigm shift in the sense that for the first time in the industry, the case for higher density is not clear in view of associated cost.